ASIC Design Verification Engineer || Verilog, UVM, Testbench | Emulation || Exp 7+ years
BengaluruFull-time7–13 yrsPosted 2 weeks ago
Senior electrical and electronics role at Cisco in Bengaluru. Needs 7+ years and a PhD.
About the role
You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.
What you'll do
- As a Design Verification Engineer specializing in Simulation & Emulation
- Your primary focus will be on emulation platforms to accelerate verification cycles and improve coverage
- Develop and implement verification plans and test benches using emulation tools and methodologies
- Collaborate with design and validation teams to identify verification requirements and coverage goals
- Utilize emulation platforms to run large-scale verification tests and debug design issues
What you need
- UVM
- VLSI
- Verilog
- Test cases
- Routing and switching