ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
PuneFull-time8–12 yrsPosted over a month ago
Leadership electrical and electronics role at Cisco in Pune. Needs 8–12 years.
About the role
Understand and implement verification scenarios per full chip analog and digital verification test plans Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs FW/C-Coding and verification of CPU sub-systems with FW
What you'll do
- Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs
What you need
- C
- UVM
- Verilog
- Python
- Test cases