DFT ASIC Engineering Technical Leader | ATPG | 10 to 14 years | Bangalore
BengaluruFull-time10–14 yrsPosted over a month ago
Leadership electrical and electronics role at Cisco in Bengaluru. Needs 10–14 years.
About the role
Supervise implementation of ATPG, scan compression, memory BIST, and other advanced DFT techniques to improve test coverage and efficiency. Guide the debugging and root-cause analysis of silicon failures, leveraging team expertise to improve yield and reliability.
What you'll do
- Collaborate with chip architects, design engineers, and verification teams to define, optimize, and standardize DFT strategies across multiple projects
- Supervise implementation of ATPG, scan compression, memory BIST, and other advanced DFT techniques to improve test coverage and efficiency
- Guide the debugging and root-cause analysis of silicon failures, leveraging team expertise to improve yield and reliability
What you need
- Root cause analysis