Senior Design Verification Engineer

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

What you'll do

• Define comprehensive verification strategies, test architectures, and detailed test plans covering full chip, subsystem, and block levels
• Architect scalable SystemVerilog and Universal Verification Methodology (UVM) verification environments with constrained-random stimulus generation, protocol checkers
• Establish bit-accurate reference models using C/C++ integrated via Direct Programming Interface (DPI)-C to verify complex pixel-processing algorithms and video pipelines…
• Verify high-speed protocol interfaces and link layers against industry standards, including packetization, link training, error management, and recovery mechanisms
• If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

What you need

• UVM
• Python
• Perl
• C
• C++
• Verilog

Good to have

• Test cases