Senior Design Lead
ChennaiFull-time5–7 yrsPosted 1 week ago
Senior design role at HCLTech in Chennai. Needs 5–7 years and a B.Tech or B.E..
About the role
Candidates with 5 to 7 years experience is mandatory Has participated in multiple ASIC/SoC verification till tapeout stage Full chip TB Architecture definition Experience writing ASIC/SoC testplans 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
What you'll do
- C based TB development
- Test case development, coding, execution, bug analysis
- Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic
- 3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues
What you need
- UVM
- Verilog
- Perl
- Shell scripting
- VLSI
- Linux
Good to have
- Python
- Test cases
- C