Technical Architect
IndiaFull-time10–18 yrsPosted 1 week ago
Leadership software engineering role at HCLTech. Needs 10+ years and a B.Tech or B.E..
About the role
We are seeking a Principal / Staff Physical Verification Engineer with 10+ years of experience to drive the full-chip layout verification strategy and manufacturing sign-off for our next-generation, high-performance SoCs.
What you'll do
- Lead the definition, deployment, and execution of full-chip hierarchical physical verification methodologies (DRC, LVS, ERC, ESD, Antenna, and DFM)
- Serve as the primary technical interface with leading silicon foundries (e.g., TSMC, Intel, Samsung). Critically evaluate, customize
- Architect clean database aggregation models. Standardize layout hand-offs between third-party IPs, mixed-signal blocks, digital subsystems
- Troubleshoot, root-cause, and debug the most complex full-chip structural violations—such as massive LVS text-shorts, complex soft-check loops
- Establish and enforce strict corporate-wide physical verification waiver policies. Conduct formal layout sign-off reviews and audit block-level violations to minimize…
What you need
- Python
- VLSI
- Perl