Technical Architect
IndiaFull-timeSenior levelPosted 1 week ago
Senior software engineering role at HCLTech.
About the role
We are seeking a senior Full-Chip Low Power Verification / VCLP Engineer to lead the architectural integration and static low-power sign-off for massive, complex multi-core SoCs. In this role, you will be responsible for defining the hierarchical Unified Power Format ( UPF ) strategy and executing Synopsys VC LP at the full-chip level.
What you'll do
- Troubleshoot and root-cause complex VC LP structural errors and warnings, including missing isolation cells, incorrect level shifter ranges, mismatched power domains
- 1.Low power design Techniques
- Dynamic Voltage and Frequency Scaling (DVFS)
- Synopsys VC LP (or equivalent static low-power checkers) or Cadence Conformal LP or Siemens Questa LP
What you need
- Python
- Perl
- VBA