Technical Architect

About the role

We are seeking an expert Full-Chip TFM CAD Physical Design Engineer to own, architect, and optimize our digital implementation and sign-off flow environments. In this role, you will design robust, enterprise-grade automated pipelines that control the full layout lifecycle—from hierarchical floorplanning and logic synthesis to clock tree synthesis, routing, timing closure, and tape-out sign-off.

What you'll do

• Define, build, and deploy the automated hierarchical RTL-to-GDSII execution flows used across all block-level and full-chip integration platforms
• Evaluate and introduce next-generation EDA features, including AI-driven optimization engines, advanced routing techniques, and hierarchical physical synthesis
• Standardize database hand-offs, data structures, and revision controls between IPs, subsystems, and the top-level full-chip environment
• Set up, calibrate, and automate critical full-chip sign-off tracks, including Static Timing Analysis (STA), Electromigration & IR Drop (EMIR)
• Scale the CAD environment to support massive, multi-billion transistor designs. Drive regressions using distributed grid computing (HPC) with high memory-to-runtime…

What you need

• Python
• Git
• Docker
• VLSI
• Data structures
• Perl

Good to have

• Linux