Senior Engineer II - Verification

About the role

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization?

What you'll do

• Define verification plans and build testbenches using UVM/System Verilog for PCIe Gen5/6/7 IP
• Integrate and configure third-party PCIe Verification IPs (e.g., Synopsys, Cadence) for Gen5/6/7 verification
• Develop test cases, checkers, and functional/code coverage models per the verification plan
• Collaborate with firmware, emulation, and silicon validation teams; support pre-silicon and post-silicon bring-up/debug

What you need

• UVM
• Verilog
• Test cases