Senior High Speed IO Validation Engineer

About the role

We are hiring an HSIO Validation Engineer to own characterization and qualification of high-speed I/Os — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet — on brand-new silicon serving datacenter, AI, and client markets. Your bench is where silicon meets the signal — where every link train, jitter sweep, eye diagram, and protocol corner gets exercised before the part ships.

What you'll do

• Develop and execute validation test plans for silicon and SoC-level HSIO features — bring-up, corner qualification, stress, productization
• Drive power characterization and optimization across IO interconnects under workload-representative stimuli (MLPerf-class patterns at silicon/board level) — analyze…
• Drive systematic root-cause analysis for complex HSIO bugs — isolating contributions across silicon, package, board, firmware, and driver
• Convert rack-observed failures into silicon/board reproducers so future spins fix the root cause upstream
• Assess manufacturing and yield implications of HSIO margin distributions — identify gaps in scaling from chip to product, and feed back into binning and design

What you need

• Instrumentation
• Python
• Test cases
• Root cause analysis
• Test automation

Good to have

• Circuit design