DDR PHY Senior Digital Design Engineer
BengaluruFull-time3–6 yrsPosted over a month ago
Mid-level electrical and electronics role at Qualcomm in Bengaluru. Needs 3+ years and a B.Sc, B.Tech or B.E..
About the role
We are seeking a motivated and technically strong DDR PHY Digital Design Engineer to join our team working on next-generation memory interface IPs. The candidate will be responsible for the architecture, RTL implementation, verification support, synthesis, low-power design, DFT, and silicon bring-up of high-performance DDR PHY solutions used in leading-edge SoC products.
What you'll do
- Design and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces
- Participate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs
- Drive RTL quality and signoff through lint, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power, and design rule checks
- Collaborate with the functional verification team to develop verification plans, review coverage closure, and debug design issues
- Develop synthesis and timing constraints, analyze timing reports, and deliver high-quality netlists for physical design implementation
What you need
- VLSI
- Verilog