NPU/AI Processor Synthesis (Design implementation) - Staff Engineer
Bengaluru, HyderabadFull-time18–30 yrsPosted over a month ago
Leadership electrical and electronics role at Qualcomm in Bengaluru and Hyderabad. Needs 18+ years and a B.Sc, B.Tech or B.E..
About the role
We are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.
What you'll do
- Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems
- Develop and maintain synthesis flows, constraints, and automation for complex hierarchical designs
- Drive pre-layout and post-layout timing closure across multiple modes and process corners
- Optimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies
- Create, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths
What you need
- VLSI
- Python
- Travel booking
- Perl
- Machine learning
- Verilog