NPU Design implementation (Synthesis) Principal/Manager
Bengaluru, HyderabadFull-time4–7 yrsPosted over a month ago
Mid-level electrical and electronics role at Qualcomm in Bengaluru and Hyderabad. Needs 4+ years and a B.Sc, B.Tech or B.E..
About the role
The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.
What you'll do
- Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus)
- Develop and maintain synthesis scripts and flows for hierarchical and flat designs
- Drive pre-layout and post-layout timing closure across multiple voltage and process corners
- Collaborate with STA teams to resolve setup/hold violations
- Power & Area Optimization
What you need
- VLSI
- Python
- Perl
- Verilog