Staff/ Senior Staff Engineer, STA
BengaluruFull-time7–13 yrsPosted 2 weeks ago
Senior mechanical and production role at Renesas JP in Bengaluru. Needs 7+ years and a B.Tech, B.E. or M.Tech.
About the role
We are looking for a highly motivated STA Engineer to join our VLSI design team. The ideal candidate will be responsible for driving timing closure and signoff readiness for block-level and full-chip designs across all operating modes and process corners.
What you'll do
- Perform block-level and full-chip Static Timing Analysis (STA) across all modes and corners in MMMC environments
- Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations
- Develop, validate, and maintain timing constraints, including SDC creation, review, and signoff readiness
- Partner closely with RTL Design, Synthesis, CTS, Physical Design, and Signoff teams to achieve timing closure goals
- Drive timing closure through ECO implementation, timing optimization, and timing convergence activities
What you need
- VLSI
- Perl
- Python
- Verilog