Senior Design Formal Verification Engineer
HyderabadFull-time4–7 yrsPosted 1 week ago
Mid-level electrical and electronics role at SiFive in Hyderabad. Needs 4+ years.
About the role
We are seeking a Senior Design Formal Verification Engineer to own blocks and apply formal strategies for out‑of‑order (OoO) CPU cores . You will work closely with micro‑architects and RTL designers to signoff some of the complex blocks using formal.
What you'll do
- Identify blocks suitable for applying Formal Verification
- Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics
- Implementation and maintenance of Formal Verification environments in Chisel
- Applying various FV techniques to reduce complexity and prove correctness of DUT
- Debugging RTL to identify causes of failure scenarios
What you need
- Verilog
- Maintenance
- Test cases