SOC Design Verification Engineer
AhmedabadFull-time5–15 yrsPosted 1 week ago
Senior electrical and electronics role at UST in Ahmedabad. Needs 5+ years.
About the role
SOC Design Verification Engineer at UST. Own end-to-end verification activities for complex IPs, subsystems, and SoCs, from specification analysis through verification sign-off.
What you'll do
- Own end-to-end verification activities for complex IPs, subsystems, and SoCs, from specification analysis through verification sign-off
- Design and develop scalable, reusable SystemVerilog/UVM-based testbench environments
- Define verification strategies, develop test plans, and drive functional coverage and verification closure
- Debug complex design issues, perform root-cause analysis, and collaborate with design and architecture teams
- Develop assertions, scoreboards, reference models, reusable VIPs, and automation scripts
What you need
- UVM
- Verilog
- C
- Python
- Perl
- Test cases
Good to have
- Root cause analysis
- VLSI