Technical Lead I - VLSI STA SD
BengaluruFull-time5–7 yrsPosted 1 week ago
Senior software engineering role at UST in Bengaluru. Needs 5–7 years.
About the role
Around 5-8 years of minimum exp in Synthesis/Constraints Development and Validation/Timing Closure and Sign-off ( blocks/fullchip) Complete Ownership of Subsystem level STA closure, Includes giving feedback to PnR owner Hands on experience with PrimeTime is must.
What you need
- VLSI
- Perl