Technical Lead I - VLSI
Bengaluru, HyderabadFull-time5–7 yrsPosted 1 week ago
Senior software engineering role at UST in Bengaluru and Hyderabad. Needs 5–7 years.
About the role
We are seeking a skilled FPGA RTL Design Engineer with 4+ years of experience in FPGA development and digital design. The candidate will be responsible for RTL design, implementation, verification, and FPGA bring-up for high-performance SoC/FPGA-based solutions.
What you'll do
- Design and develop RTL using Verilog/SystemVerilog/VHDL for FPGA-based applications
- Perform FPGA synthesis, place & route, timing closure, and performance optimization
- Develop and execute functional verification plans, testbenches, and debugging activities
- Collaborate with hardware, firmware, and system teams for integration and validation
- Analyze and resolve design, timing, and FPGA implementation issues
What you need
- VLSI
- FPGA
- Verilog