Design Verification Lead
BengaluruFull-time7–13 yrsPosted over a month ago
Senior electrical and electronics role at Weekday AI in Bengaluru. Needs 7+ years.
About the role
We are looking for an experienced Senior Design Verification Engineer with strong expertise in SystemVerilog (SV) and UVM-based verification to drive verification activities for complex IP and SoC designs.
What you'll do
- Develop and execute comprehensive design verification strategies and plans for IP and SoC projects
- Translate functional and technical requirements into detailed verification plans, test scenarios, and coverage objectives
- Develop scalable and reusable SystemVerilog/UVM verification environments
- Build UVM components including testbenches, agents, drivers, monitors, sequencers, scoreboards, and coverage models
- Set up, configure, execute, and debug functional and gate-level simulations
What you need
- UVM
- Verilog
- Test cases
Good to have
- Python
- Perl