Full-Chip STA Signoff Engineer
HyderabadFull-time6–17 yrs14 L–₹32 L a yearPosted 2 months ago
Senior electrical and electronics role at Weekday AI in Hyderabad. Needs 6+ years and a B.Tech, B.E. or M.Tech. Pays ₹14–32 LPA.
About the role
We are looking for an experienced Full-Chip STA Signoff Engineer with 6–17 years of hands-on experience in Static Timing Analysis and timing closure for complex SoC designs. The ideal candidate will have strong expertise in full-chip STA signoff , timing analysis, constraint development, timing closure, and signoff methodologies across advanced semiconductor process nodes.
What you'll do
- Own and execute full-chip Static Timing Analysis (STA) signoff for complex SoC designs
- Perform timing analysis across multiple modes and corners (MMMC) and ensure complete timing coverage
- Analyze setup, hold, recovery, removal, minimum pulse width, clock gating, and other timing checks
- Develop, review, and maintain timing constraints including SDC, clocks, generated clocks, input/output delays, false paths, multicycle paths, and clock uncertainty
- Debug and resolve timing violations across functional and test modes
What you need
- VLSI
- Python
- Perl