Lead RTL Engineer ( Mixed-Signal IPs)
HyderabadFull-time5–10 yrsPosted over a month ago
Senior electrical and electronics role at Silabs in Hyderabad. Needs 5+ years and a B.Tech, B.E. or M.Tech.
About the role
The RTL Design Engineer for Mixed-Signal IPs is responsible for developing, integrating, and verifying digital RTL blocks within mixed-signal subsystems that combine analog and digital functionalities. This role requires a deep understanding of digital design principles, interface with analog/mixed-signal teams, and strong verification and integration skills to ensure high-quality, low-power, and functionally robust IP delivery.
What you'll do
- Develop synthesizable, high-quality RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends
- Collaborate with analog design engineers to define digital-analog interface specifications, control logic, and communication protocols
- Ensure correct functionality and performance of mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components
- Participate in design reviews, micro-architecture definition, and documentation of IP functionality and timing interfaces
- Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses
What you need
- Verilog
- Python
- Circuit design
- Calibration
- Perl
- Test cases