ASIC Digital Design, Staff Engineer
BengaluruFull-time4–8 yrsPosted 3 months ago
Senior electrical and electronics role at Synopsys (incl. Ansys) in Bengaluru. Needs 4+ years and a B.Tech or B.E..
About the role
ASIC Digital Design, Staff Engineer at Synopsys (incl. Ansys). Build and maintain UVM-based testbench for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors.
What you'll do
- Build and maintain UVM-based testbench for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors
- Write System Verilog test cases and constrained random stimulus to verify functional correctness across different operating modes and protocol scenarios
- Develop and execute verification plans based on design specifications, identifying test scenarios, corner cases, and coverage goals
- Debug RTL and testbench issues by analyzing simulation logs, waveforms, and coverage reports to isolate root causes and verify fixes
- Implement assertion-based checks and functional coverage models to track verification progress and ensure thorough validation
What you need
- UVM
- Verilog
- Python
- Test cases
- Shell scripting
- Perl
Good to have
- Git
- Customer success