ASIC Digital Design, Staff Engineer
BengaluruFull-time4–7 yrsPosted over a month ago
Mid-level electrical and electronics role at Synopsys (incl. Ansys) in Bengaluru. Needs 4+ years and a B.Tech, B.E. or M.Tech.
About the role
ASIC Digital Design, Staff Engineer at Synopsys (incl. Ansys). Architect and implement RTL designs for DesignWare IP cores targeting commercial, enterprise, and automotive applications.
What you'll do
- Architect and implement RTL designs for DesignWare IP cores targeting commercial, enterprise, and automotive applications
- Own hands-on RTL coding in synthesizable Verilog/SystemVerilog for medium to high complexity features, including data path logic like Reed Solomon FEC, BCH codes
- Drive synthesis, static timing analysis, CDC analysis, lint checking, and P&R-aware synthesis using tools like Fusion Compiler, ensuring designs meet area, latency
- Collaborate with global engineering teams and engage directly with customers to refine specifications, resolve design ambiguities, and align on feature requirements
- Lead technical reviews, debug complex RTL issues across simulation and synthesis, and develop test strategies that ensure design quality and coverage
What you need
- Verilog
- VLSI
- Perl
- Shell scripting