ASIC Digital Design, Staff Engineer
BengaluruFull-time6–11 yrsPosted 2 months ago
Senior electrical and electronics role at Synopsys (incl. Ansys) in Bengaluru. Needs 6+ years and a B.Tech or B.E..
About the role
ASIC Digital Design, Staff Engineer at Synopsys (incl. Ansys). Design and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic.
What you'll do
- Design and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic
- Translate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe
- Build and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs
- Perform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams
- Drive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows
What you need
- Verilog
- VLSI
- Perl
- Test cases