LPDDR IP Design Senior Staff Engineer - 16586
BengaluruFull-time6–11 yrsPosted open since mar 2026
Senior electrical and electronics role at Synopsys (incl. Ansys) in Bengaluru. Needs 6+ years and a B.Sc, B.Tech or B.E..
About the role
In this role, you will be in a leadership role to contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.
What you'll do
- Designing and micro-architecting LPDDR PHY IP writing Verilog and SystemVerilog code and design specification
- Conduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members
- Analyzing and fixing Lint, CDC/RDC, DFT, Timing, and power issues
- Maintain and improve design automating flow and process
What you need
- Verilog