Principal Engineer - ASIC Digital Design (Memory Interface IP- HBM/DDR/LPDDR)

About the role

Principal Engineer - ASIC Digital Design (Memory Interface IP- HBM/DDR/LPDDR) at Synopsys (incl. Ansys). Design and own complex RTL blocks for HBM, DDR, and LPDDR memory interface IP, from architecture through implementation and verification handoff.

What you'll do

• Design and own complex RTL blocks for HBM, DDR, and LPDDR memory interface IP, from architecture through implementation and verification handoff
• Collaborate directly with analog design teams to define and validate mixed-signal interfaces, ensuring timing closure and signal integrity across the full IP stack
• Develop and execute detailed verification plans in partnership with the verification team, including corner case analysis and protocol compliance testing
• Lead technical reviews and design audits, providing clear direction on architecture tradeoffs and implementation risks
• Mentor engineers on the team, reviewing RTL code, guiding design decisions, and helping them build the judgment that separates working designs from great ones

What you need

• Circuit design
• VLSI
• Verilog
• UVM