R&D Engineering, Principal Engineer-19515
BengaluruFull-time15–27 yrsPosted 1 week ago
Leadership electrical and electronics role at Synopsys (incl. Ansys) in Bengaluru. Needs 15+ years.
About the role
R&D Engineering, Principal Engineer-19515 at Synopsys (incl. Ansys). Own timing signoff methodology for standard cell libraries across TSMC N3, N2, N5, N7, and derivative nodes, defining setup, hold, recovery, removal, pulse-width.
What you'll do
- Own timing signoff methodology for standard cell libraries across TSMC N3, N2, N5, N7, and derivative nodes, defining setup, hold, recovery, removal, pulse-width
- Develop and validate multi-corner, multi-mode signoff flows for low-VDD, high-performance, and AI/compute SoCs, accounting for AOCV, POCV, SOCV, aging effects
- Drive correlation analysis between Liberty models, PrimeTime STA results, HSPICE simulations
- Debug critical customer-reported timing issues, root-cause discrepancies between characterization, signoff, and deployment
- Build automation infrastructure in Python and Tcl to scale signoff validation, quality checks, and methodology deployment across multiple library releases
What you need
- VLSI
- Python
- Linux