ASIC Verification Engineer

About the role

Debug Regression failures in RTL and Gatelevel simulations, analyze Functional Coverage gaps and improve tests to cover the gaps Document verification strategy including Test plans, Testbench, Random tests, etc.

What you'll do

• Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features
• Develop verification environments using System Verilog and UVM
• Architect and develop scalable and re-usable test benches, using the framework of the verification methodology
• Develop BFMs / Checkers / monitors / Scoreboards
• Build pseudo-random tests to verify and get full Functional coverage

What you need

• 8–14 years in electrical & electronics
• UVM
• Verilog
• Test cases
• B.Tech or B.E.

Good to have

• SAS