- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to:
What you'll do
- Be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems
- Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area
- Close work with Layout and Floor planning teams
What you need
- 10–18 years in electrical & electronics
- Circuit design
- VLSI
- B.Tech or B.E.
Good to have
- Verilog
- Python
- Perl
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- Can I apply
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- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site