CPU RTL Design Manager

About the role

The manager will own end-to-end execution of the MEU cluster across RTL Design, Design Verification, and Formal Verification, driving feature development from architecture definition through RTL implementation, pre-silicon validation, quality signoff, and silicon readiness.

What you'll do

• Own end-to-end delivery of the MEU cluster across RTL, DV, and Formal Verification functions
• Drive microarchitecture reviews, implementation strategy, verification closure, and quality signoff
• Ensure delivery of features meeting Power, Performance, Area (PPA), Quality, Reliability, and Security objectives
• Define execution strategy, milestones, risk mitigation plans, and resource allocation
• Drive adoption of advanced methodologies, automation, AI-assisted debug, formal technologies, and verification innovations

What you need

• 15–27 years in electrical & electronics
• Verilog
• VLSI
• B.Tech or B.E.

Good to have

• Machine learning