CPU Senior Floor Plan Engineer

About the role

Defines the physical dimensions of the CPU IP with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Performs integration of all dies in a package and completes the relevant checks before tape out.

What you'll do

• In this role you will be responsible for all the aspects of Floorplan and pin placement activities
• Engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle
• Work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan
• Play critical role in die size estimation and in evaluating Floorplan tools, methods and flows
• Planning boundaries and pin densities to facilitate high confidence timing closure and routability

What you need

• 4–7 years in electrical & electronics
• VLSI
• Power systems
• B.Tech or B.E.

Good to have

• Python
• Perl