Design Verification Engineer II

About the role

We are looking for a design verification engineer to work in the dynamic Microsoft Artificial Intelligence S ilicon Engineering ( AIS iE ) team. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

What you'll do

• The AISiE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered…
• Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
• Develop tests using UVM or C/C++
• Analyse and debug test failures with designers to deliver functionally correct design

What you need

• 3–6 years in electrical & electronics
• UVM
• C++
• Verilog
• Python
• Perl
• C
• Any graduate

Good to have

• Test cases