Design Verification Engineer

About the role

As a Design Verification Engineer at Analog Devices, you will develop verification environments and execute verification activities for next-generation automotive connectivity SoCs based on E2B technology. You will work on complex devices incorporating embedded processors, digital communication subsystems, firmware, security functions, and mixed-signal components.

What you'll do

• Verification Environment Development: Develop and maintain SystemVerilog /UVM verification environments, including agents, sequences, monitors, scoreboards
• Test Development: Develop directed and constrained-random tests for block-level, subsystem-level, and SoC-level verification
• Cross-Functional Collaboration: Work with design, architecture, firmware, functional safety, validation

What you need

• 2–4 years in electrical & electronics
• UVM
• Verilog
• C
• Python
• Perl
• Embedded C
• B.Tech or B.E.

Good to have

• FPGA
• Prototyping
• Test cases