DFT Timing Lead

About the role

As a key member of the S3 SoC DFT Team, the successful candidate will play a significant role in ensuring the quality of next generation AMD SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.

What you'll do

• Develop full chip DFT Synthesis and DFT STA constraints
• STA constraint development of DFT modes (ScanShift, Atspeed, MBIST)
• Set up DFT timing constraints, defining the overall SOC Test STA methodology
• Working with the Design team to clean-up all the DFT related constraint issues
• Closely work with physical design team to generate and validate timing constraints

What you need

• 8–15 years in electrical & electronics
• VLSI
• AWS
• B.Tech or B.E. or M.Tech