Engineer - Physical design

About the role

We are looking for a Physical Engineer specialized in building with 1–2 years of relevant experience to join our SoC implementation team. You will contribute to next-generation SoC projects, working across the synthesis-to-GDSII flow. This role offers hands-on experience in physical implementation, timing analysis, debugging and power, performance and area (PPA) optimization.

What you'll do

• Complete and support RTL synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and GDSII generation with mentorship from senior engineers
• Analyze and improve PPA through synthesis and physical implementation
• Conduct static timing analysis with Synopsys PrimeTime, troubleshoot setup and hold violations, and assist in achieving timing closure across operating modes and corners
• Review timing constraints, tool reports and implementation results to identify issues, investigate root causes and propose fixes
• Assist with physical verification and final approval processes, including DRC, LVS, signal integrity, and EM/IR analysis

What you need

• 1–2 years in electrical & electronics
• VLSI
• Python
• Power systems
• Verilog
• Linux
• B.Tech or B.E.