Functional Verification Engineer

About the role

Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.

What you'll do

• Expected to be an SME, collaborate and manage the team to perform
• Responsible for team decisions
• Engage with multiple teams and contribute on key decisions
• Provide solutions to problems for their immediate team and across multiple teams
• Lead efforts to improve verification methodologies and processes to enhance efficiency and coverage

What you need

• 5–9 years in electrical & electronics
• UVM
• Embedded C
• Verilog
• Any graduate

What you get