Functional Verification Engineer

About the role

Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.

What you'll do

• Expected to perform independently and become an SME
• Required active participation/contribution in team discussions
• Contribute in providing solutions to work related problems
• Develop and maintain verification environments to support design validation efforts
• Analyze verification results and debug issues to improve test coverage and quality

What you need

• 3–6 years in electrical & electronics
• Verilog
• Test cases
• UVM
• Any graduate

What you get