IP/Subsystem Verification Lead

About the role

As a Principal Design Verification Engineer, you will lead the verification efforts to functionally verify complex RTL blocks and SOCs destined for the next generation of Data Center networking ASICs RTL design experience would be an advantage. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.

What you'll do

• Lead the verification efforts to functionally verify complex RTL blocks and SOCs destined for the next generation of Data Center networking ASICs

What you need

• 15–27 years in electrical & electronics
• FPGA
• Verilog
• UVM
• Any graduate

Good to have

• C++
• VLSI
• Python
• C