Layout Design, Staff Engineer- 19592

About the role

Layout Design, Staff Engineer- 19592 at Synopsys (incl. Ansys). Lead layout development for cutting edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies.

What you'll do

• Lead layout development for cutting edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies
• Own floorplanning, layout matching, ESD design, latch-up mitigation, and DFM compliance for analog and mixed-signal blocks that have to work in silicon
• Drive layout reviews, quality checks, PERC and EMIR analysis, and release processes that meet both internal standards and customer requirements
• Mentor junior layout engineers through hands-on technical leadership, teaching them how to solve real problems in deep submicron design
• Collaborate with cross-functional teams including analog designers, verification engineers, and foundry partners to meet project timelines and deliver best-in-class IP

What you need

• 5–9 years in electrical & electronics
• VLSI
• B.Tech or B.E. or M.Tech