- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
Proficient in Verilog coding and RTL design, data path designs, Familiar with synthesis flow and timing constraints Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display
What you need
- 6–10 years in electrical & electronics
- Verilog
- Any graduate
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- Can I apply
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- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site