- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
Design verification of ASICs for Palladium. Will have to work at IP, Sub-System and SOC level verification. Test plan creation, functional coverage plan and coding of functional coverage bins. Will be involved in post silicon validation/bring up.
What you'll do
- Design verification of ASICs for Palladium
- Test plan creation, functional coverage plan and coding of functional coverage bins
What you need
- 4–7 years in electrical & electronics
- UVM
- Verilog
- Test cases
- B.Sc or M.Sc or B.Tech or B.E.
Similar jobs
- Can I apply
- Needs PhD · 8–14 yrs
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- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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- Can I apply
- Open to any education · 5–8 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Applied Materials' site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site