- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
Be part of the Cadence DDR PHY IP Front End Design team responsible for -
What you'll do
- Develop firmware for DDR5 PHY using microcontrollers
- Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers
- Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them
- Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan
- Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)
What you need
- 6–10 years in electrical & electronics
- Embedded C
- C
- Python
- Perl
- Verilog
- Any graduate
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- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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- How to apply
- On Applied Materials' site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site