Lead Design Engineer

About the role

Lead Design Engineer at Cadence. Have design responsibility, including floor planning, power grid design, place and route, clock tree synthesis, timing/SI closure, power / EM-IR signoff.

What you'll do

• Physical design for PPA optimization of performance and power-oriented best-in-class interface IPs such as DDR, LPDDR, PCIE, UCIE
• An opportunity to work on many varieties of challenging designs, i.e., low power, high-speed and area optimized designs
• Work closely with RTL design team & Analog Team to ensure on-time, successful tapeouts

What you need

• 4–6 years in electrical & electronics
• VLSI
• Python
• Perl
• Verilog
• B.Tech or B.E. or M.Tech