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Lead Design Engineer

Cadence·Pune

Pay not stated4–8 yrsFull-time
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About the role

The DV Architect is a senior technical leadership role responsible for the strategic vision and infrastructure of verification for next-generation Tensilica advanced CPU cores and configurable processors. You will define the methodologies that ensure the functional integrity of highly complex instruction set architectures (ISA).

What you'll do

  • Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements
  • Define the methodologies that ensure the functional integrity of highly complex instruction set architectures (ISA)

What you need

  • 4–8 years in electrical & electronics
  • C++
  • UVM
  • C
  • Verilog
  • Python
  • Perl
  • B.Tech or B.E. or M.Tech

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