- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
We at AECG SSD Custom Silicon are seeking a highly motivated and experienced Full-Chip Floorplan Engineer to drive physical implementation planning for complex SoCs and ASICs.
What you'll do
- Define chip aspect ratio, die size, partitioning strategy, and hierarchy planning
- Perform macro placement and optimization for timing, congestion, power, and thermal considerations
- Drive floorplan refinement through design milestones
- Define floorplan topology for large-scale SoCs containing multiple subsystems, hard IPs, memories, and third-party IPs
- Collaborate with package teams on bump map optimization
What you need
- 12–22 years in electrical & electronics
- VLSI
- B.Tech or B.E. or M.Tech
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- Pay
- Pay not stated
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- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site