Lead Hardware Engineer - DFT IP R&D

About the role

MODUS is a complete product that encompasses Design for Test Solution for Achieving High Coverage, Reduced Test Time, and Superior PPA. The product breadth means we are looking for skilled and motivated candidates with backgrounds in RTL design, DFT architecture, computer architecture, verification, RTL compilation, placement, static timing analysis, power analysis, routing, extraction, and optimization.

What you'll do

• Play a key role in developing cutting-edge design-for-testability (DFT) tools
• Designing and verifying Verilog/SystemVerilog/UVM RTL and test benches for DFT IP features, including new DFT IPs, full scan, compressed/uncompressed scan, memory BIST
• Providing R&D support to application and product engineers, including problem analysis, debugging
• Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their problem-solving…

What you need

• 4–6 years in electrical & electronics
• Hardware
• Verilog
• VLSI
• Data structures
• UVM
• Troubleshooting
• B.Tech or B.E. or M.Tech

Good to have

• Python
• Perl