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Lead Solutions Engineer

Cadence·Bengaluru

Pay not statedSenior levelFull-time
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About the role

Understand/review Design specification and develop verification strategy/Test plan/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Developing c-based test cases for SOC verification.

What you'll do

  • Writing tests/sequences/functional coverage/assertions to meet verification goals
  • Developing c-based test cases for SOC verification

What you need

  • 6–10 years in electrical & electronics
  • Verilog
  • UVM
  • C++
  • Embedded C
  • C
  • Python
  • Any graduate

Good to have

  • Test cases
  • Perl

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