Lead STA Engineer

About the role

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet rigorous criteria for achieving Right-First-Time silicon. The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners.

What you'll do

• Responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners
• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness

What you need

• 15–27 years in electrical & electronics
• VLSI
• Python
• Perl
• Any graduate