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LEC/CLP Engineer

AMD·Hyderabad

Pay not stated6–11 yrsFull-time
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About the role

MTS LEC and CLP SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan and execute the LEC and CLP of IP Subsystems and its signoff. This involves ownership of LEC and CLP at all physical partition level. Responsible for LEC and CLP of all physical partitions of a device including its waivers, reviews and signoff Collaborate and support with design and/or implementation teams to achieve closure.

What you'll do

  • Responsible for LEC and CLP of all physical partitions of a device including its waivers
  • Drive this activity with set of engineers by planning work and presenting regular status

What you need

  • 6–11 years in electrical & electronics
  • B.Tech or B.E.

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