- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
What you'll do
- Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology
- Be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks
What you need
- 2–5 years in electrical & electronics
- Verilog
- B.Tech or B.E. or M.Tech
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Early: posted 1 h ago on their own site
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- Can I apply
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- How to apply
- On Applied Materials' site (Workday): account needed, ~10–15 min
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- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site